Multistandard video decoder

ABSTRACT

A system and method for processing video are disclosed. The method may include, in a chip, parsing an encoded video stream to determine one or more identifiers that identifies one or more corresponding CODEC to be utilized for decoding one or more corresponding portions of said encoded video stream. Corresponding portions of the encoded video stream may be decoded utilizing the identified one or more corresponding CODECs. The corresponding portions of the encoded video stream may be concurrently decoded utilizing the identified one or more corresponding CODECs. The one or more corresponding CODECs to be utilized for the decoding of the one or more corresponding portions of the encoded video stream may be selected from a plurality of CODECs.

RELATED APPLICATIONS

This application makes reference to, claims priority to, and claims thebenefit of U.S. Provisional Patent Application 60/573,357 (AttorneyDocket number 15747US01), filed on May 21, 2004 and entitled“Multistandard Video Decoder,” the complete subject matter of which ishereby incorporated herein by reference in its entirety.

This application is related to the following applications, each of whichis incorporated herein by reference in its entirety for all purposes:

-   U.S. patent application Ser. No. 10/963,677 (Attorney Docket No.    15748US02) filed Oct. 13, 2004;-   U.S. patent application Ser. No. 10/985,501 (Attorney Docket No.    15749US02) filed Nov. 10, 2004;-   U.S. patent application Ser. No. ______ (Attorney Docket No.    15750US02) filed ______, 2004;-   U.S. patent application Ser. No. 10/985,110 (Attorney Docket No.    15751 US02) filed Nov. 10, 2004;-   U.S. patent application Ser. No. 10/981,218 (Attorney Docket No.    15754US02) filed Nov. 4, 2004;-   U.S. patent application Ser. No. 10/965,172 (Attorney Docket No.    15756US02) filed Oct. 13, 2004;-   U.S. patent application Ser. No. 10/972,931 (Attorney Docket No.    15757US02) filed Oct. 25, 2004;-   U.S. patent application Ser. No. 10/974,179 (Attorney Docket No.    15759US02) filed Oct. 27, 2004;-   U.S. patent application Ser. No. 10/974,872 (Attorney Docket No.    15760US02) filed Oct. 27, 2004;-   U.S. patent application Ser. No. 10/970,923 (Attorney Docket No.    15761 US02) filed Oct. 21, 2004;-   U.S. patent application Ser. No. 10/963,680 (Attorney Docket No.    15762US02) filed Oct. 13, 2004;-   U.S. patent application Ser. No. ______ (Attorney Docket No.    15763US02) filed ______, 2004;-   U.S. patent application Ser. No. ______ (Attorney Docket No.    15792US01) filed ______, 2004;-   U.S. patent application Ser. No. ______ (Attorney Docket No.    15810US02) filed ______, 2004; and-   U.S. patent application Ser. No. ______ (Attorney Docket No.    15811US02) filed ______, 2004.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[Not Applicable]

BACKGROUND OF THE INVENTION

During encoding of a video signal, one or more encoding techniques, suchas H.261, H.263, H.263+ (Annex J), H.264, SMPTE VC-1, MPEG-1, MPEG-2and/or MPEG-4, may be utilized to encode the video signal on amacroblock-by-macroblock basis. During encoding of video information,for example, prediction error information may be encoded together withprediction mode information, as well as with other side informationnecessary for the decoding process. In order to encode the predictionerror information, a discrete cosine transformation may be applied totransform the prediction error information into frequency domaincoefficients prior to quantization and entropy encoding. During thisprocess, certain information relating to the prediction error, forexample, may be lost. As a result of the missing information, thequality of the decoded video signal may be decreased. More specifically,transform blockiness may appear in the decoded video in the form ofsquare grid artifacts, for example. Other artifacts may also appear inthe decoded video due to missing video information.

Conventional video decoders are adapted to decode elementary videostream encoded according to a single encoding standard, such as H.264,VC-1, MPEG-1, MPEG-2 and/or MPEG-4 encoding standards. An elementaryvideo stream may be encoded utilizing a single encoding technique.However, an application space may support a stream being encoded usingany one of many standards. For example, the Blu-Ray ROM specificationfor high definition DVD playback allows a video stream to be encodedusing MPEG-2, H.264, or VC-1.

However, decoding efficiency in conventional video processing systems issubstantially decreased since two or more decoders may need to beutilized for processing/decoding of elementary video streams that mayhave been encoded according to different encoding standards.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of ordinary skill in the artthrough comparison of such systems with the present invention as setforth in the remainder of the present application with reference to thedrawings.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor processing an encoded video stream. Aspects of the method maycomprise receiving on a chip, packetized data within the encoded videostream. An identifier within the received packetized data may bedetermined on the chip, where the identifier may define one of aplurality of encoding types associated with packets in the encoded videostream. A decoding process may be selected on the chip from a pluralityof decoding processes, based on the determined identifier. A portion ofthe received packetized data in the encoded video stream may be decodedon the chip utilizing the selected decoding process. A delimiter may bedetermined within the received packetized data that separates packetswithin the encoded video stream. A plurality of bytes within thereceived packetized data may be matched with a determined byte sequence.If the plurality of bytes matches the determined byte sequence, theplurality of bytes may be removed from the received packetized data.

If the determined identifier corresponds to H.264 video encoding, thereceived packetized data may be decoded utilizing a fixed length coding(FLC) process, a variable length coding (VLC) process and/or a contextadaptive binary arithmetic coding (CABAC) process. If the determinedidentifier corresponds to VC-1, H.261, H.263, H.263+, MPEG-1, MPEG-2and/or MPEG-4 video encoding, the received packetized data may bedecoded utilizing a FLC process and/or a VLC process. The decodedpacketized data may comprise decoding process control information and/orprediction error information. A decoded video stream may be generatedutilizing the decoded packetized data. The generated decoded videostream may be filtered utilizing an overlapped transform process and/ora deblocking process. For each of the plurality of decoding processes, aportion of the received packetized data may be decoded on the chiputilizing inverse transformation, inverse quantization, and/or motioncompensation.

Another embodiment of the invention may provide a machine-readablestorage, having stored thereon, a computer program having at least onecode section executable by a machine, thereby causing the machine toperform the steps as described above for processing an encoded videostream.

Aspects of the system may comprise at least one processor that receiveson a chip, packetized data within the encoded video stream on a chip.The processor may determine on the chip an identifier within thereceived packetized data that defines one of a plurality of encodingtypes associated with packets in the encoded video stream. A decodingprocess may be selected by the processor from a plurality of decodingprocesses based on the determined identifier. A portion of the receivedpacketized data in the encoded video stream may be decoded by theprocessor utilizing the selected decoding process. A delimiter withinthe received packetized data that separates packets within the encodedvideo stream may be determined by the processor. The processor may matcha plurality of bytes within the received packetized data with adetermined byte sequence and if the plurality of bytes matches thedetermined byte sequence, the plurality of bytes may be removed by theprocessor from the received packetized data.

If the determined identifier corresponds to H.264 video encoding, thereceived packetized data may be decoded by the processor utilizing afixed length coding (FLC) process, a variable length coding (VLC)process and/or a context adaptive binary arithmetic coding (CABAC)process. If the determined identifier corresponds to VC-1, H.261, H.263,H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video encoding, the receivedpacketized data may be decoded by the processor utilizing a FLC processand/or a VLC process. The decoded packetized data may comprise decodingprocess control and/or prediction error information. A decoded videostream may be generated by the processor utilizing the decodedpacketized data. The processor may filter the generated decoded videostream utilizing an overlapped transform process and/or a deblockingprocess.

These and other features and advantages of the present invention may beappreciated from a review of the following detailed description of thepresent invention, along with the accompanying figures in which likereference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an encapsulated video payload with adelimiter, in accordance with an embodiment of the invention.

FIG. 2 is a block diagram illustrating byte destuffing within elementaryvideo stream data, in accordance with an embodiment of the invention.

FIG. 3A is a high level block diagram illustrating a multistandard videodecoder, in accordance with an embodiment of the invention.

FIG. 3B is a high level block diagram illustrating a multistandard videodecoder utilizing a single CPU, in accordance with an embodiment of theinvention.

FIG. 3C is a high level block diagram illustrating a multistandard videodecoder utilizing a CPU pair, in accordance with an embodiment of theinvention.

FIG. 4A is a block diagram illustrating a multistandard video decoderwith hardware assist blocks and a single CPU, in accordance with anembodiment of the invention.

FIG. 4B is a block diagram illustrating a multistandard video decoderwith hardware assist blocks and a CPU pair, in accordance with anembodiment of the invention.

FIG. 5 is a block diagram illustrating operation of the multistandardvideo decoder of FIG. 4 when decoding H.264 video data, in accordancewith an embodiment of the invention.

FIG. 6 is a block diagram illustrating operation of the multistandardvideo decoder of FIG. 4 when decoding VC-1 video data, in accordancewith an embodiment of the invention.

FIG. 7 is a block diagram illustrating operation of the multistandardvideo decoder of FIG. 4 when decoding MPEG-1 or MPEG-2 video data, inaccordance with an embodiment of the invention.

FIG. 8 is a block diagram illustrating operation of the multistandardvideo decoder of FIG. 4 when decoding MPEG-4 video data, in accordancewith an embodiment of the invention.

FIG. 9 is a flow diagram of an exemplary method for processing anencoded video stream, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system forprocessing an encoded video stream. During encoding of a video stream,different encoding standards may be utilized to encode data withinelementary video streams. In one aspect of the invention, amultistandard video decoder may be adapted to acquire an elementaryvideo stream encoded according to an encoding standards, such as H.261,H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or MPEG-4, forexample. The multistandard decoder may locate one or more delimiterswithin the elementary video stream, where the delimiters may separatepacketized data within encapsulated video payloads. Each delimiter maycomprise a start code information signaling the beginning of a videopayload and an encoding type information.

The encoding type information may be associated with a method ofencoding utilized by an encoder to encode a corresponding video payload.The multistandard decoder may also destuff, or remove, one or more bytesfrom the encapsulated video payload, where such bytes were inserted byan encoder to avoid false start codes from being present in the videopayload. Depending on the encoding type information, the encapsulatedvideo payload may be decoded on-chip utilizing corresponding decodingmodules. For example, temporal or spatial prediction pixels may begenerated from decoding process control information in the encapsulatedvideo payload. In addition, prediction errors may also be generated fromquantized frequency coefficients within the encoded video payload. Adecoded video stream may then be reconstructed utilizing temporal and/orspatial prediction pixels and prediction error information. In oneaspect of the invention, the multistandard decoder may utilize a singlecentral processing unit (CPU) to process header information andmacroblock information within the packets in the encoded bitstream. Inanother aspect of the invention, a CPU pair may be utilized, where afirst CPU may process future header information while a second CPU mayprocess current macroblock information.

FIG. 1 is a block diagram of an encapsulated video payload 100 with adelimiter, in accordance with an embodiment of the invention. Referringto FIG. 1, the encapsulated video payload 100 may comprise a delimiter104 and elementary video stream data 105. The delimiter 104 may comprisea start code 101 and a start code suffix 103 and may be utilized by adecoder, for example, to locate a starting bit for the encapsulatedvideo payload 100 as well as a starting bit for the elementary videostream data 105. In addition, the delimiter 104 may comprise informationrelating to the method of encoding utilized to encode the elementaryvideo stream data 105. The elementary video stream data may comprise aplurality of bytes, where each byte may comprise two nibbles.

The start code 101 may comprise a plurality of bytes that may bearranged in a unique combination to signify the beginning of theencapsulated video payload 100 within an encoded video stream. Forexample, the start code 101 may comprise an exemplary byte sequence “0000 01.” The start code suffix 103 may comprise one or more bytes locatedafter the start code 101 within the encapsulated video payload 100. Inone aspect of the invention, the start code suffix 103 may correspond toan encoding method utilized to encode the elementary video stream data105 within the encapsulated video payload 100. For example, the startcode suffix 103 may correspond to H.264, VC-1, MPEG-1, MPEG-2 and/orMPEG-4 as the encoding method utilized to encode the elementary videostream data 105. The start code 101 and the start code suffix 103 may begenerated by the encoder prior to communicating the encoded video streamdata to a video decoder.

FIG. 2 is a block diagram illustrating byte destuffing within elementaryvideo stream data 200, in accordance with an embodiment of theinvention. Referring to FIG. 2, the elementary video stream data 200 maycomprise elementary video data sequences 201 and 203. The elementaryvideo stream data 200 may be preceded by a delimiter comprising a startcode sequence and a start code suffix, as illustrated on FIG. 1. Duringvideo signal encoding and after an encoder has generated a delimiter forthe elementary video stream data 200, the encoder may insert one or morebytes in the elementary video stream data 200 so that a correspondingstart code sequence may not be recognized by a decoder within theelementary video stream data 200 during decoding.

For example, during encoding of the elementary video stream data 200, anencoder may utilize a start code comprising the byte sequence “00 0001.” During decoding of the elementary video stream 200, a decoder mayincorrectly identify the start code sequence “00 00 01” within theelementary stream 200. In order to avoid any such mis-identification ofa start code sequence, an encoder may insert one or more extracharacters/symbols, or a stuffing byte, so that a start code sequencemay not be mis-identified within the elementary video stream 200 duringdecoding. For example, an extra character string, or a stuffing byte,“03” may be inserted within the byte sequence 205 within the elementaryvideo data sequence 201. Similarly, the stuffing byte “03” may also beinserted within the byte sequence 207 within the elementary video datasequence 203. In this manner, the decoder may be prevented fromrecognizing the start code sequence “00 00 01” during decoding of theelementary video stream 200.

During decoding of the elementary video stream 200, a video decoder maydestuff or remove, any extra characters inserted in the elementary videostream 200 during encoding. Accordingly, the extra character string “03”may be removed from the byte sequence 205 within the elementary videodata sequence 201, and the extra character “2” may be removed from thebyte sequence 207 within the elementary video data sequence 207. In thismanner, a raw video payload may be generated after removing any extracharacters within the elementary video stream 200. The resulting rawvideo payload may then be decoded by a symbol interpreter, for example.

FIG. 3A is a high level block diagram illustrating a multistandard videodecoder, in accordance with an embodiment of the invention. Referring toFIG. 3A, the multistandard video decoder 300 may comprise a memory block301, a code-in-port (CIP) 305, a stream parser 307, and a processingblock 303. The CIP 305 comprises suitable circuitry, logic and/or codeand may be adapted to acquire an elementary video stream 309. The CIP305 may also be adapted to locate start codes and start code suffixeswithin the elementary video stream 309 and to destuff extra bytes fromthe elementary video stream 309, thus generating raw elementary videostream.

The multistandard video decoder 300 may utilize the stream parser 307 toprocess start code information and raw stream information that may beacquired from the CIP 305. For example, the stream parser 307 may beadapted to process header information and/or macroblock information fromthe raw elementary bitstream generated by the CIP 305. Headerinformation from the raw elementary bitstream may comprise sliceinformation, picture information, GOP/entry point information, and/orsequence information, for example. Slice packets within the rawelementary video stream generated by the CIP 305 may comprise sliceheader information and macroblock information corresponding to theparticular slice. In addition, the stream parser 307 may be adapted toprocess header and/or macroblock information in the raw elementarystream acquired from the CIP 305, and generate quantized frequencycoefficients information and/or additional side information, forexample, necessary for decoding of macroblock information in the rawelementary video stream.

The stream parser 307 may comprise one or more decoder assist blocksspecific to each mode of encoding that may be utilized to decode the rawelementary stream. The output signal from the stream parser 307 may becommunicated to the processing block 303 via the bus 311. The bus 311may be implemented within the multistandard video decoder 300 as aone-way bus communicating information to the processing block 303 toincrease processing efficiency and simplicity of implementation.Temporary information generated during decoding of the raw elementaryvideo stream may be stored by the stream parser 307 and/or by the CIP305 in the memory module 301. The memory module 301 may comprise DRAM,for example.

In an exemplary aspect of the invention, the stream parser 307 may beimplemented utilizing a single CPU and a single corresponding symbolinterpreter (SI). The single CPU/SI configuration may be utilized toprocess the entire video elementary stream, including startcodes/suffixes, header information, and/or macroblock information. Inanother aspect of the invention, the stream parser 307 may beimplemented utilizing two separate CPUs and symbol interpreters forincreased processing efficiency. For example, in the exemplarydual-CPU/SI configuration, a first CPU and a first SI may be utilized toprocess header information within the elementary video stream, and asecond CPU with a corresponding second SI may be utilized to processmacroblock information from the elementary bitstream. In this regard,subsequent header information may be processed by the first CPU and thefirst SI, while the second CPU and the second SI may simultaneouslyprocess current macroblock information.

The processing block 303 may utilize the processing informationgenerated by the stream parser 307 to generate a decoded video stream313. The processing block 303 comprises suitable circuitry, logic and/orcode and may be adapted to perform one or more of the followingprocessing tasks: spatial prediction, motion compensation, inversequantization and transformation, macroblock reconstruction, in-loopmacroblock filtering, and/or macroblock post processing. Each of theprocessing tasks within the processing block 303 may utilize one or moreassist blocks corresponding to a specific encoding method that may havebeen utilized to encode the elementary video stream 309. In this regard,the processing block 303 may be adapted to decode an elementary videostream that may have been encoded utilizing one of a plurality ofencoding methods, such as H.261, H.263, H.263+(Annex J), H.264, VC-1,MPEG-1, MPEG-2 and/or MPEG-4, for example.

FIG. 3B is a high level block diagram illustrating a multistandard videodecoder 320 utilizing a single CPU, in accordance with an embodiment ofthe invention. Referring to FIG. 3B, the multistandard video decoder 320may comprise a memory block 321, a code-in-port (CIP) 329, an inner loopcentral processing unit (ILCPU) 325, an inner loop symbol interpreter(ILSI) 327, and a processing block 323. The CIP 329 comprises suitablecircuitry, logic and/or code and may be adapted to acquire an elementaryvideo stream 331. The CIP 329 may also be adapted to locate start codesand/or start code suffixes within the elementary video stream 331 and todestuff extra bytes from the elementary video stream 331, thusgenerating raw elementary video stream.

In an exemplary embodiment of the invention, the multistandard videodecoder 320 may utilize the ILCPU 325 and the ILSI 327 to process headerinformation and/or macroblock information from the raw elementarybitstream generated by the CIP 329. Header information from the rawelementary bitstream may comprise slice information, pictureinformation, GOP/entry point information, and/or sequence information,for example. Slice packets within the raw elementary video streamgenerated by the CIP 329 may comprise slice header information and/ormacroblock information corresponding to the particular slice.

The ILSI 327 comprises suitable circuitry, logic and/or code and may beadapted to process header and/or macroblock information in the rawelementary stream acquired from the CIP 329, and generate quantizedfrequency coefficients information and/or additional side information,for example, necessary for decoding of macroblock information in the rawelementary video stream. The ILSI 327 may comprise one or more decoderassist blocks specific to each mode of encoding that may be utilized todecode the raw elementary stream.

The ILCPU 325 may be adapted to sequence the ILSI 327 by, for example,providing decoding instructions to the ILSI 327 via the bus 333. The bus333 may be implemented within the multistandard video decoder 320 as aone-way bus communicating information to the processing block 323 toincrease processing efficiency and simplicity of implementation.Temporary information generated during decoding of the raw elementaryvideo stream may be stored by the ILCPU 325, the CIP 329, and/or theILSI 327 in the memory module 321. The memory module 321 may compriseDRAM, for example.

In operation, the incoming elementary video stream 331 may comprisevideo data encoded according to one of a plurality of encodingstandards, such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1,MPEG-2, and/or MPEG-4, for example. The CIP 329 may be adapted to detectone or more start codes and start code suffixes, which may correspond tothe mode of encoding of the elementary video stream 331. The CIP 329 mayalso be adapted to generate a raw elementary video stream comprisingheader and/or macroblock information. The start codes and the rawelementary stream may be communicated, via the memory 321, to the ILCPU325 and the ILSI 327 for further processing. The ILSI 327, utilizinginstructions from the ILCPU 325, may be adapted to process the headerand/or macroblock information communicated by the CIP 329. The ILSI 327may then generate an output signal that may comprise acquired macroblocktype information, slice type information, prediction mode information,motion vector information, and/or quantized frequency coefficients, forexample. The output signal may be communicated via the bus 333 to theprocessing block 323 for use during macroblock decoding.

The processing block 323 may utilize the processing informationgenerated by the ILSI 327 to generate a decoded video stream 335. Theprocessing block 323 comprises suitable circuitry, logic and/or code andmay be adapted to perform one or more of the following processing tasks:spatial prediction, motion compensation, inverse quantization andtransformation, macroblock reconstruction, in-loop macroblock filtering,and/or macroblock post processing. Each of the processing tasks withinthe processing block 323 may utilize one or more assist blockscorresponding to a specific encoding method that may have been utilizedto encode the elementary video stream 331. In this regard, theprocessing block 323 may be adapted to decode an elementary video streamthat may have been encoded utilizing one of a plurality of encodingmethods, such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1,MPEG-2, and/or MPEG-4, for example.

FIG. 3C is a high level block diagram illustrating a multistandard videodecoder 340 utilizing a CPU pair, in accordance with an embodiment ofthe invention. Referring to FIG. 3C, the multistandard video decoder 340may comprise a memory block 341, an outer loop central processing unit(OLCPU) 349, a code-in-port (CIP) 351, an outer loop symbol interpreter(OLSI) 353, an inner loop central processing unit (ILCPU) 345, an innerloop symbol interpreter (ILSI) 347, and a processing block 343. The CIP351 comprises suitable circuitry, logic and/or code and may be adaptedto acquire an elementary video stream 355. The CIP 351 may also beadapted to locate start codes and start code suffixes within theelementary video stream 355 and to destuff extra bytes from theelementary video stream 355, thus generating raw elementary videostream.

In an exemplary embodiment of the invention, the multistandard videodecoder 340 may utilize a CPU pair, such as ILCPU 345 and OLCPU 349,with corresponding ILSI 347 and OLSI 353, to separately process headerinformation and macroblock information from the raw elementary bitstreamgenerated by the CIP 351. Header information from the raw elementarybitstream may comprise slice information, picture information, GOP/entrypoint information, and/or sequence information, for example. Slicepackets within the raw elementary video stream generated by the CIP 351may comprise slice header information and macroblock informationcorresponding to the particular slice. For example, the OLCPU 349 andthe OLSI 353 may be adapted to process header information from the rawelementary bitstream generated by the CIP 351. In addition, the ILCPU345 and the ILSI 347 may be adapted to process macroblock informationfrom the raw elementary bitstream generated by the CIP 351. In thismanner, parallel processing may be achieved within the multistandardvideo decoder 340 as the OLCPU 349 and the OLSI 353 may process futureheader information, while the ILCPU 345 and the ILSI 347 may processcurrent macroblock information.

The ILSI 347 comprises suitable circuitry, logic and/or code and may beadapted to process macroblock information in the raw elementary streamacquired from the CIP 351, and generate quantized frequency coefficientsinformation and/or additional side information, for example, necessaryfor decoding of macroblock information in the raw elementary videostream. The ILSI 347 may comprise one or more decoder assist blocksspecific to each mode of encoding that may be utilized to decode the rawelementary stream. The OLSI 353 comprises suitable circuitry, logicand/or code and may be adapted to process header information in the rawelementary stream acquired from the CIP 351.

The ILCPU 345 may be adapted to sequence the ILSI 347 by, for example,providing decoding instructions to the ILSI 347 via the bus 357. The bus357 may be implemented within the multistandard video decoder 340 as aone-way bus communicating information to the processing block 343 toincrease processing efficiency and simplicity of implementation.Temporary information generated during decoding of the raw elementaryvideo stream may be stored by the ILCPU 345, the OLCPU 349, the OLSI353, the CIP 351, and/or the ILSI 347 in the memory module 341. Thememory module 341 may comprise DRAM, for example.

In operation, the incoming elementary video stream 355 may comprisevideo data encoded according to one of a plurality of encodingstandards, such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1,MPEG-2, and/or MPEG-4, for example. The CIP 351 may be adapted to detectone or more start codes and start code suffixes, which may correspond tothe mode of encoding of the elementary video stream 355. The CIP 351 mayalso be adapted to generate a raw elementary video stream comprisingheader and/or macroblock information. Header information within the rawelementary stream generated by the CIP 351 may be communicated to theOLCPU 349 and the OLSI 353 for further processing. The start codes andmacroblock information within the raw elementary stream may becommunicated, via the memory 341, to the ILCPU 345 and the ILSI 347 forfurther processing. In an exemplary aspect of the invention, the OLCPU349 and the OLSI 353 may be adapted to process subsequent, or future,header information, while the ILCPU 345 and the ILSI 347 may processcurrent macroblock information.

The ILSI 347, utilizing instructions from the ILCPU 345, may be adaptedto process the macroblock information in the raw elementary streamcommunicated by the CIP 351. The ILSI 347 may then generate an outputsignal that may comprise acquired macroblock type information, slicetype information, prediction mode information, motion vectorinformation, and/or quantized frequency coefficients, for example. Theoutput signal may be communicated via the bus 357 to the processingblock 343 for use during macroblock decoding.

The processing block 343 may utilize the processing informationgenerated by the ILSI 347 to generate a decoded video stream 361. Theprocessing block 343 comprises suitable circuitry, logic and/or code andmay be adapted to perform one or more of the following processing tasks:spatial prediction, motion compensation, inverse quantization andtransformation, macroblock reconstruction, in-loop macroblock filtering,and/or macroblock post processing. Each of the processing tasks withinthe processing block 343 may utilize one or more assist blockscorresponding to a specific encoding method that may have been utilizedto encode the elementary video stream 355. In this regard, theprocessing block 343 may be adapted to decode an elementary video streamthat may have been encoded utilizing one of a plurality of encodingmethods, such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1,MPEG-2 and/or MPEG-4, for example.

FIG. 4A is a block diagram illustrating a multistandard video decoderwith hardware assist blocks and a single CPU, in accordance with anembodiment of the invention. Referring to FIG. 4A, the multistandardvideo decoder 400 may comprise a code-in-port (CIP) 403, a symbolinterpreter 405, a central processing unit (CPU) 407, a spatialprediction block 409, an inverse quantization and transformation (IQT)block 411, a motion compensation block 413, a reconstructor 415, anin-loop filter 417, a frame buffer 419 and a post-processing block 421.

The CIP 403 comprises suitable circuitry, logic and/or code and may beadapted to receive video elementary code stream 401 and generate startcodes, start code suffixes and raw elementary stream. The CIP 403 maycomprise a start code finding block 423 and a byte destuffing block 425.The start code finding block 423 may be adapted to locate start codesand start code suffixes, as illustrated in FIG. 1. The byte destuffingblock 425 may be adapted to destuff extra bytes from the videoelementary codestream 401 and generate raw elementary stream data, asillustrated in FIG. 2. After the start codes, start code suffixes andraw elementary stream are generated within the CIP 403, the start codesuffixes 426 may be communicated to the CPU 407 and the raw elementarystream may be communicated to the symbol interpreter 405 for furtherprocessing.

In an exemplary embodiment of the invention, the multistandard videodecoder 400 may utilize the CPU 407 and the symbol interpreter 405 toprocess header information and/or macroblock information from the rawelementary bitstream generated by the CIP 403. Header information fromthe raw elementary bitstream may comprise slice information, pictureinformation, GOP/entry point information, and/or sequence information,for example. Slice packets within the raw elementary video streamgenerated by the CIP 403 may comprise slice header information andmacroblock information corresponding to the particular slice.

The symbol interpreter 405 comprises suitable circuitry, logic and/orcode and may be adapted to interpret raw elementary stream 424 acquiredfrom the CIP 403 to obtain quantized frequency coefficients informationand/or additional side information necessary for decoding of the rawelementary video stream 424. The symbol interpreter 405 may alsocommunicate to the CPU 407, video information on subsequent macroblockand/or frame within the raw elementary video stream 424 via theconnection 406. After the CPU 407 acquires start code suffixes 426 fromthe CIP 403, the CPU 407 may generate one or more decoding instructionsfor the symbol interpreter 405 based on the encoding method associatedwith the acquired start code suffixes 426. The CPU 407 may be adapted tosequence the symbol interpreter 405 by providing such decodinginstructions to the symbol interpreter 405 via the connection 408. TheCPU 407 may also communicate decoding instructions to the symbolinterpreter 405 based on received video information on a subsequentmacroblock and/or frame via the connection 406.

In one aspect of the invention, the incoming elementary video stream 401may comprise video data encoded according to one of a plurality ofencoding standards, such as H.261, H.263, H.263+(Annex J), H.264, VC-1,MPEG-1, MPEG-2 and/or MPEG-4, for example. The symbol interpreter 405,utilizing instructions from the CPU 407, may be adapted to decode one ormore symbols and/or additional processing information, such as headerand/or macroblock information, that may be utilized to complete decodingof the raw elementary stream 424 received from the CIP 403. The symbolinterpreter 405 may comprise a plurality of decoder assist blocksspecific to each mode of encoding that may be utilized to decode the rawelementary stream 424.

In an illustrative embodiment of the invention, the symbol interpreter405 may comprise a fixed length coding (FLC) block 427, a variablelength coding (VLC) block 429, a context adaptive binary arithmeticcoding (CABAC) block 433, a coefficient construction block 435, and avector construction block 437. The decoder assist blocks within thesymbol interpreter 405 may be utilized during decoding depending onencoding method information that may be obtained from a start codesuffix 426 generated by the CIP 403 and communicated to the CPU 407. TheFLC block 427, the VLC block 429 and the CABAC block 433 may be utilizedby the symbol interpreter 405 to decode/interpret single syntax elementsfrom the raw elementary stream 424 that were encoded utilizing fixedlength coding, variable length coding or CABAC coding techniques,respectively.

The coefficient construction block 435 may be adapted to generate one ormore quantized frequency coefficients from the raw elementary stream424. Quantized frequency coefficients generated by the coefficientconstruction block 435 may be subsequently utilized within themultistandard video decoder 400 to generate prediction error informationutilized during reconstruction of one or more macroblocks. The generatedquantized frequency coefficients may be communicated by the symbolinterpreter 405 to the IQT block 411 for further processing.

Similarly, the vector construction block 437 may be adapted to generateone or more motion vectors from the raw elementary stream 424. Themotion vectors generated by the vector construction block 437 may beutilized within the multistandard video decoder 400 to generateprediction pixels utilized during reconstruction of one or moremacroblocks. The generated motion vector information may be communicatedby the symbol interpreter 405 to the motion compensation block 413 forfurther processing.

The spatial prediction block 409 comprises suitable circuitry, logicand/or code and may be adapted to generate prediction pixels used by thereconstruction block 415 to generate a decoded macroblock. The spatialprediction block 409 may be adapted to acquire macroblock typeinformation, slice type information and/or prediction mode information,for example, from the symbol interpreter 405. The spatial predictionblock 409 may then utilize the acquired macroblock type information,slice type information and/or prediction mode information to generateprediction pixels for spatially predicted macroblocks.

The motion compensation block 413 comprises suitable circuitry, logicand/or code and may be adapted to generate prediction pixels utilizingmotion vector information received from the symbol interpreter 405. Forexample, the motion compensation block 413 may generate predictionpixels for temporally predicted macroblocks, which may be associatedwith motion compensation vectors in frames/fields neighboring a currentframe/field. The motion compensation block 413 may acquire previousand/or subsequent frames/fields from the frame buffer 419 and utilizethe acquired previous and/or subsequent frames/fields for predictingtemporally encoded pixels within a current macroblock.

The motion compensation block 413 may comprise a plurality of motioncompensation assist blocks that may be utilized to generate theprediction pixels depending on the method utilized to encode the rawelementary stream data 424. For example, the motion compensation block413 may comprise a range remap block 447, an intensity compensationblock 449, an interpolation block 451, a variable block sizing module453, and bi-directional prediction block 455. The interpolation block451 may be adapted to interpolate one or more prediction pixels within acurrent frame utilizing motion vector information received from thesymbol interpreter 405, as well as one or more reference frames that aretemporally adjacent to the current frame.

If prediction pixels are interpolated utilizing only one referenceframe, the interpolation block 451 may be utilized to generate theprediction pixels. However, if more than one prediction reference framesare utilized during temporal prediction of a current pixel, thebi-directional prediction block 455 may be utilized by the motioncompensation block 413 to generate the prediction pixels. For example,if several reference frames are utilized for prediction of a currentpixel, the bi-directional prediction block 455 may determine the currentprediction pixel as an average of the prediction pixels in the referenceframes.

The range remap block 447 may be utilized by the motion compensationblock 413 during decoding of a VC-1 encoded raw elementary stream. Morespecifically, the range remap block 447 may be utilized to remap thedynamic range of a reference frame prior to interpolation by theinterpolation block 451. The intensity compensation block 449 may beutilized by the motion compensation block 413 to adjust the intensitylevel of a reference frame to the intensity level of a current frameprior to interpolation by the interpolation block 451

The variable block sizing module 453 may be utilized by the motioncompensation block 413 to control utilization of reference framesacquired from the frame buffer 419. For example, the variable blocksizing module 453 may fetch a 16×16, 16×8 and/or 4×4 pixel sizemacroblock from the frame buffer 419 for use during temporal predictionof pixels within a current macroblock. Other macroblock and/or framesizes may also be supported by the frame buffer 419, as may be requiredduring motion compensation prediction within the motion compensationblock 413.

The IQT block 411 comprises suitable circuitry, logic and/or code andmay be adapted to transform quantized frequency coefficients receivedfrom the symbol interpreter 405 into one or more prediction errors. Morespecifically, the IQT block 411 may be adapted to utilize the inversequantization block 443 and the inverse transformation block 445 totransform the quantized frequency coefficients back to spatial domain,thus generating prediction error information. The prediction errorinformation generated by the IQT block 411 may then be communicated tothe reconstructor 415 for further processing during reconstruction of amacroblock.

The inverse zigzag block 439 may be utilized by the IQT block 411 torearrange the quantized frequency coefficients received from the symbolinterpreter 405 prior to inverse transformation by the inversetransformation block 445. Quantized frequency coefficients generated bythe symbol interpreter 405 may have been arranged in a zigzag scan orderto facilitate encoding. Accordingly, the inverse zigzag block 439 mayutilize one or more look-up tables to arrange the quantized frequencycoefficients in sequential order, for example.

Depending on the encoding method of the raw elementary stream 424, theIQT block 411 may utilize an AC/DC prediction block 441 during decodingof the prediction error information. For example, quantized frequencycoefficients may be encoded within the raw elementary stream 424utilizing prediction residuals and prediction errors from neighboringpixels. Further, DC prediction within the AC/DC prediction block 441 maycorrespond to zero frequency coefficients utilized for generatingprediction error information. AC prediction within the AC/DC predictionblock 441 may correspond to low frequency coefficients utilized forgenerating prediction error information. Additional information on theoperation of a symbol interpreter, motion compensation block, spatialprediction block and inverse quantization and transformation block ismore fully disclosed in U.S. patent application Ser. No. 10/963,677(Attorney Docket No. 15748US02) filed Oct. 13, 2004, which isincorporated herein by reference in its entirety.

The reconstructor 415 may be adapted to acquire spatial predictionpixels or temporal prediction pixels from the spatial prediction block409 or the motion compensation block 413, respectively. In addition, thereconstructor 415 may be adapted to acquire prediction error informationgenerated by the IQT block 411. The reconstructor 415 may thenreconstruct a current macroblock utilizing prediction pixels andprediction error information. The reconstructed macroblock may becommunicated to the in-loop filter 417 for further processing.

The in-loop filter 417 comprises suitable circuitry, logic and/or codeand may be adapted to further filter a decoded/reconstructed macroblockthat may be acquired from the reconstructor 415. Depending on theencoding method of the raw elementary stream 424, the in-loop filter 417may comprise an overlapped transformation block 457 and a deblockingmodule 459. The overlapped transformation block 457 may be utilizedduring filtering of a macroblock generated from a VC-1 encoded rawelementary stream 424. More specifically the overlapped transformationblock 457 may apply an overlapped transformation to a reconstructedmacroblock in order to reduce edge artifacts along one or more edges ofthe reconstructed macroblock. Similarly, the deblocking module 459 mayalso be utilized by the in-loop filter 417 to reduce edge artifacts andtransform blockiness effects along one or more edges of a reconstructedmacroblock. Additional information on deblocking and deblocking memoryutilization within a decoder is more fully disclosed in U.S. patentapplication Ser. No. 10/965,172 (Attorney Docket No. 15756US02) filedOct. 13, 2004 and U.S. patent application Ser. No. 10/972,931 (AttorneyDocket No. 15757US02) filed Oct. 25, 2004, which are incorporated hereinby reference in their entirety.

After a reconstructed macroblock is filtered by the in-loop filter 417,additional post-processing may be performed by the post-processing block421. Depending on the encoding method of the raw elementary stream 424,the post-processing block may utilize one or more of the followingpost-processing assist blocks: a range remapping block 461, a resizingblock 463, a deblocking module 465 and/or a deringing block 467. Therange remapping block 461 may be utilized by the post-processing block421 if during a VC-1 encoding process, the dynamic range of amacroblock, or a series of macroblocks, was changed. In this manner, alldecoded macroblocks 469 that are communicated to a display postprocessorare characterized by the same dynamic range.

The resizing block 463 may be utilized by the post-processing block 421to rescale/resize a macroblock that may have been upscaled or downscaledduring encoding. By utilizing the resizing block 463, thepost-processing block 421 may generate decoded macroblocks 469 with thesame resolution. The deringing block 467 may be utilized to attenuate“mosquito noise” within a reconstructed macroblock that may have beengenerated by overly quantized AC coefficients. The deblocking module 465is similar to the deblocking module 459 within the in-loop filter 417,and may be utilized to further reduce edge artifacts and transformblockiness effects along one or more edges of a reconstructed macroblockprior to communication of the macroblock to a display post-processor,for example.

FIG. 4B is a block diagram illustrating a multistandard video decoderwith hardware assist blocks and a CPU pair, in accordance with anembodiment of the invention. Referring to FIG. 4B, the multistandardvideo decoder 470 may comprise a code in port (CIP) 471, an outer loopCPU (OLCPU) 473, an outer loop symbol interpreter (OLSI) 475, an innerloop CPU (ILCPU) 477, and an inner loop symbol interpreter (ILCPU) 479.The multistandard video decoder 470 may also comprise a spatialprediction block, an inverse quantization and transformation block, amotion compensation block, a reconstruction block, an in-loop filteringblock, frame buffers block, and/or a post-processing block (not picturedin FIG. 4B), as illustrated and described in detail with regard to themultistandard video decoder 400 in FIG. 4A.

In an exemplary embodiment of the invention, the multistandard decoder470 may utilize the OLCPU 473 and OLSI 475 to process header informationfrom the video elementary bitstream 480. The ILCPU 477 and ILSI 479 maybe utilized to process macroblock information from the video elementarybitstream 480. In this manner, parallel processing may be achievedwithin the multistandard video decoder 470 as OLCPU 473 and OLSI 475 maybe processing future header information while ILCPU 477 and ILSI 479 maybe processing current macroblock information. Header information fromthe elementary bitstream 480 may comprise slice information, pictureinformation, GOP/entry point information, and/or sequence information,for example.

In operation, the CIP 471 may receive video elementary code stream 480and generate start codes and start code suffixes 481 and raw elementarystream 482. The start codes and start code suffixes 481 may becommunicated for processing to the OL CPU 473 and the raw packetsinformation 482 may be communicated for processing to the OLSI 475. TheOLCPU 473 and the OLSI 475 may be adapted to process only headerinformation from the start codes and start code suffixes 481 and the rawelementary stream 482. The OLCPU 473 may interface with an off-chipvideo processing system, for example, via the system communications port483.

The OLSI 475 may comprise a variable length coding (VLC) block 484 and afixed length coding (FLC) block 472. The VLC block 484 and the FLC block472 may be utilized to decode header information from the raw packetsinformation 482 received from the CIP 471. For example, headerinformation 485 may be extracted from the raw packets information 482,thus generating an output bitstream 486. The output bitstream 486 maycomprise macroblock-related information and may be communicated to theILSI 479 for further processing. After OLCPU 473 processes headerinformation from the start codes and start code suffixes information481, the resulting processing control information 476 may becommunicated for further processing to the ILCPU 477. The processingcontrol information 476 may comprise control information correspondingto packets containing macroblock information, such as packets in theoutput bitstream 486.

The ILCPU 477 and the ILSI 479 may be adapted to simultaneously processmacroblock-related information for a current macroblock while the OLCPU473 and the OLSI 475 may be processing subsequent header information.The ILSI 479, similarly to the symbol interpreter 405 in FIG. 4A, may beadapted to generate an output signal 487. The output signal 487 maycomprise acquired macroblock type information, slice type information,prediction mode information, motion vector information, and/or quantizedfrequency coefficients, for example. The acquired macroblock typeinformation, slice type information and/or prediction mode information488 may be communicated to a spatial prediction block (not pictured),such as the spatial prediction block 409 in FIG. 4A, for furtherprocessing and generation of prediction pixels for spatially predictedmacroblocks.

The motion vector information 490 may be communicated to a motioncompensation block (not pictured), such as the motion compensation block413 in FIG. 4A, for further processing and generation of predictionpixels for temporally predicted macroblocks. The quantized frequencycoefficients 489 may be communicated to an inverse quantization andtransformation block (not pictured), such as the inverse quantizationand transformation block 411 in FIG. 4A, for further processing andgeneration of prediction errors utilized during macroblock decoding.

FIG. 5 is a block diagram illustrating operation of the multistandardvideo decoder 500 of FIG. 4 when decoding H.264 video data, inaccordance with an embodiment of the invention. Referring to FIG. 5, themultistandard video decoder 500 may be adapted to process videoelementary codestream 401 that was encoded utilizing H.264 encodingtechniques. The CIP 403 may utilize the start code finding block 423 tolocate start codes and start code suffixes, as well as the bytedestuffing block 425 to remove extra bytes from the H.264 encoded videoelementary codestream 401.

The symbol interpreter 405 may be adapted to interpret the H.264 rawelementary stream 424 acquired from the CIP 403 to obtain quantizedfrequency coefficients information and/or additional side information,such as macroblock type information, slice type information, predictionmode information, and/or motion vectors information, necessary fordecoding of the H.264 raw elementary video stream 424. During generationof the quantized frequency coefficients and/or the side information, thesymbol interpreter 405 may receive instructions by the CPU 407 andprovide subsequent symbol information to the CPU 407. In addition, thesymbol interpreter may utilize one or more of the following assistblocks: the FLC block 427, the VLC block 429, the CABAC block 433, thecoefficient construction block 435, and/or the vector construction block437.

Inverse quantized frequency coefficients may be communicated from thesymbol interpreter block 405 to the IQT block 411, which may generateprediction error information. The IQT block 411 may utilize the inversezigzag block 439, the inverse quantization block 443 and/or the inversetransformation block 445 to generate the prediction error information.Side information from the symbol interpreter 405 may be communicated toeither the spatial prediction block 409 or the motion compensation block413 to generate prediction pixels. The motion compensation block 413 mayutilize the frame buffer 419 together with the intensity compensationblock 449, the interpolation block 451, the variable block sizing module453 and/or the bi-directional prediction module 455 to generatetemporally predicted pixels.

The reconstructor 415 may then be utilized by the multistandard decoder500 to reconstruct a current macroblock utilizing prediction pixelinformation acquired from either the spatial prediction block 409 or themotion compensation block 413, respectively, as well as prediction errorinformation acquired from the IQT block 411. A reconstructed macroblockmay be filtered by the in-loop filter 417, utilizing the deblockingmodule 459. The filtered macroblock may be further processed by thepost-processing block 421. The post-processing block 421 may utilize thederinging block 467 to generate the decoded macroblock 469. The decodedmacroblock 469 may then be communicated to a display post-processor, forexample.

FIG. 6 is a block diagram illustrating operation of the multistandardvideo decoder 600 of FIG. 4 when decoding VC-1 video data, in accordancewith an embodiment of the invention. Referring to FIG. 6, themultistandard video decoder 600 may be adapted to process videoelementary codestream 401 that was encoded utilizing VC-1 encodingtechniques. The CIP 403 may utilize the start code finding block 423 tolocate start codes and start code suffixes, as well as the bytedestuffing block 425 to remove extra bytes from the VC-1 encoded videoelementary codestream 401.

The symbol interpreter 405 may be adapted to interpret the VC-1 rawelementary stream 424 acquired from the CIP 403 to obtain quantizedfrequency coefficients information and/or additional side information,such as macroblock type information, slice type information, predictionmode information, and/or motion vectors information, necessary fordecoding the VC-1 raw elementary video stream 424. During generation ofthe quantized frequency coefficients and/or the side information, thesymbol interpreter 405 may receive instructions by the CPU 407 andprovide subsequent symbol information to the CPU 407. In addition, thesymbol interpreter may utilize one or more of the following assistblocks: the FLC block 427, the VLC block 429, the coefficientconstruction block 435, and/or the vector construction block 437.

Inverse quantized frequency coefficients may be communicated from thesymbol interpreter block 405 to the IQT block 411, which may generateprediction error information. The IQT block 411 may utilize the inversezigzag block 439, the AC/DC prediction block 441, the inversequantization block 443 and/or the inverse transformation block 445 togenerate the prediction error information. Side information from thesymbol interpreter 405 may be communicated to the motion compensationblock 413 to generate prediction pixels. The motion compensation block413 may utilize the frame buffer 419 together with the intensitycompensation block 449, the range remapping block 447, the interpolationblock 451, the variable block sizing module 453 and/or thebi-directional prediction module 455 to generate temporally predictedpixels. The frame buffer 419 may be adapted to store and provide atleast two reference frames/pictures to the motion compensation block413.

The reconstructor 415 may then be utilized by the multistandard decoder600 to reconstruct a current macroblock utilizing prediction pixelinformation acquired from the motion compensation block 413, as well asprediction error information acquired from the IQT block 411. Areconstructed macroblock may be filtered by the in-loop filter 417,utilizing the deblocking module 459 and/or the overlapped transformationblock 457. The filtered macroblock may be further processed by thepost-processing block 421. The post-processing block 421 may utilize thederinging block 467, the range remapping block 461, the resizing block463, and/or the deblocking module 465 to generate the decoded macroblock469. The decoded macroblock 469 may then be communicated to a displaypost-processor, for example.

FIG. 7 is a block diagram illustrating operation of the multistandardvideo decoder 700 of FIG. 4 when decoding MPEG-1 or MPEG-2 video data,in accordance with an embodiment of the invention. Referring to FIG. 7,the multistandard video decoder 700 may be adapted to process videoelementary codestream 401 that was encoded utilizing MPEG-1 or MPEG-2encoding techniques. The CIP 403 may utilize the start code findingblock 423 to locate start codes and start code suffixes within theMPEG-1/MPEG-2 encoded video elementary codestream 401.

The symbol interpreter 405 may be adapted to interpret the MPEG-1/MPEG-2raw elementary stream 424 acquired from the CIP 403 to obtain quantizedfrequency coefficients information and/or additional side information,such as macroblock type information, slice type information, predictionmode information, and/or motion vectors information, necessary fordecoding of the MPEG-1/MPEG-2 raw elementary video stream 424. Duringgeneration of the quantized frequency coefficients and/or the sideinformation, the symbol interpreter 405 may receive instructions by theCPU 407 and provide subsequent symbol information to the CPU 407. Inaddition, the symbol interpreter may utilize one or more of thefollowing assist blocks: the FLC block 427, the VLC block 429, thecoefficient construction block 435, and/or the vector construction block437.

Inverse quantized frequency coefficients may be communicated from thesymbol interpreter block 405 to the IQT block 411, which may generateprediction error information. The IQT block 411 may utilize the inversezigzag block 439, the inverse quantization block 443 and/or the inversetransformation block 445 to generate the prediction error information.Side information from the symbol interpreter 405 may be communicated tothe motion compensation block 413 to generate prediction pixels. Themotion compensation block 413 may utilize the frame buffer 419 togetherwith the interpolation block 451, the variable block sizing module 453and/or the bi-directional prediction module 455 to generate temporallypredicted pixels. The frame buffer 419 may be adapted to store andprovide at least two reference frames/pictures to the motioncompensation block 413.

The reconstructor 415 may then be utilized by the multistandard decoder700 to reconstruct a current macroblock utilizing prediction pixelinformation acquired from the motion compensation block 413, as well asprediction error information acquired from the IQT block 411. Areconstructed macroblock may be further processed by the post-processingblock 421. The post-processing block 421 may utilize the deringing block467 and/or the deblocking module 465 to generate the decoded macroblock469. The decoded macroblock 469 may then be communicated to a displaypost-processor, for example.

FIG. 8 is a block diagram illustrating operation of the multistandardvideo decoder 800 of FIG. 4 when decoding MPEG-4 video data, inaccordance with an embodiment of the invention. Referring to FIG. 8, themultistandard video decoder 800 may be adapted to process videoelementary codestream 401 that was encoded utilizing MPEG-4 encodingtechniques. The CIP 403 may utilize the start code finding block 423 tolocate start codes and start code suffixes within the MPEG-4 encodedvideo elementary codestream 401.

The symbol interpreter 405 may be adapted to interpret the MPEG-4 rawelementary stream 424 acquired from the CIP 403 to obtain quantizedfrequency coefficients information and/or additional side information,such as macroblock type information, slice type information, predictionmode information, and/or motion vectors information, necessary fordecoding of the MPEG-4 raw elementary video stream 424. Duringgeneration of the quantized frequency coefficients and/or the sideinformation, the symbol interpreter 405 may receive instructions by theCPU 407 and provide subsequent symbol information to the CPU 407. Inaddition, the symbol interpreter may utilize one or more of thefollowing assist blocks: the FLC block 427, the VLC block 429, thecoefficient construction block 435, and/or the vector construction block437.

Inverse quantized frequency coefficients may be communicated from thesymbol interpreter block 405 to the IQT block 411, which may generateprediction error information. The IQT block 411 may utilize the inversezigzag block 439, the AC/DC prediction block 441, the inversequantization block 443 and/or the inverse transformation block 445 togenerate the prediction error information. Side information from thesymbol interpreter 405 may be communicated to the motion compensationblock 413 to generate prediction pixels. The motion compensation block413 may utilize the frame buffer 419 together with the interpolationblock 451, the variable block sizing module 453 and/or thebi-directional prediction module 455 to generate temporally predictedpixels. The frame buffer 419 may be adapted to store and provide atleast two reference frames/pictures to the motion compensation block413.

The reconstructor 415 may then be utilized by the multistandard decoder700 to reconstruct a current macroblock utilizing prediction pixelinformation acquired from the motion compensation block 413, as well asprediction error information acquired from the IQT block 411. Areconstructed macroblock may be further processed by the post-processingblock 421. The post-processing block 421 may utilize the deringing block467 and/or the deblocking module 465 to generate the decoded macroblock469. The decoded macroblock 469 may then be communicated to a displaypost-processor, for example.

FIG. 9 is a flow diagram of an exemplary method 900 for processing anencoded video stream, in accordance with an embodiment of the invention.Referring to FIG. 9, at 901, packetized data may be received withinvideo elementary code stream, where the video elementary codestream maybe encoded according to one of a plurality of encoding methods. At 903,a start code may be determined within the packetized data, where thestart code may define an encapsulated video payload. At 905, anidentifier may be determined within the packetized data that defines oneor more encoding types associated with packets in the video elementarycodestream. At 907, a decoding process may be selected from a pluralityof decoding processes based on the determined identifier. At 909, thedefined encapsulated video payload may be decoded based on the selecteddecoding process.

Accordingly, aspects of the invention may be realized in hardware,software, firmware or a combination thereof. The invention may berealized in a centralized fashion in at least one computer system, or ina distributed fashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware, software and firmware may bea general-purpose computer system with a computer program that, whenbeing loaded and executed, controls the computer system such that itcarries out the methods described herein.

One embodiment of the present invention may be implemented as a boardlevel product, as a single chip, application specific integrated circuit(ASIC), or with varying levels integrated on a single chip with otherportions of the system as separate components. The degree of integrationof the system will primarily be determined by speed and costconsiderations. Because of the sophisticated nature of modernprocessors, it is possible to utilize a commercially availableprocessor, which may be implemented external to an ASIC implementationof the present system. Alternatively, if the processor is available asan ASIC core or logic block, then the commercially available processormay be implemented as part of an ASIC device with various functionsimplemented as firmware.

The invention may also be embedded in a computer program product, whichcomprises all the features enabling the implementation of the methodsdescribed herein, and which when loaded in a computer system is able tocarry out these methods. Computer program in the present context maymean, for example, any expression, in any language, code or notation, ofa set of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform. However, other meanings of computer program within theunderstanding of those skilled in the art are also contemplated by thepresent invention.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the present inventionwill include all embodiments falling within the scope of the appendedclaims.

1-91. (canceled)
 92. A method for processing video, the methodcomprising: in a chip: parsing an encoded video stream to determine oneor more identifiers that identifies one or more corresponding CODEC tobe utilized for decoding one or more corresponding portions of saidencoded video stream; and decoding corresponding portions of saidencoded video stream utilizing said identified one or more correspondingCODECs.
 93. The method according to claim 92, comprising concurrentlydecoding said corresponding portions of said encoded video streamutilizing said identified one or more corresponding CODECs
 94. Themethod according to claim 92, comprising selecting from a plurality ofCODECs, said one or more corresponding CODECs to be utilized for saiddecoding of said one or more corresponding portions of said encodedvideo stream.
 95. The method according to claim 92, comprisingdetermining a start code within received packetized data of said encodedvideo stream, wherein said start code separates packets within saidencoded video stream.
 96. The method according to claim 95, comprisingmatching a plurality of bytes within said received packetized data witha determined byte sequence.
 97. The method according to claim 96,comprising, if said plurality of bytes matches said determined bytesequence, removing said plurality of bytes from said received packetizeddata.
 98. The method according to claim 92, comprising, if saiddetermined identifier corresponds to H.264 video encoding, decoding saidat least a portion of said received packetized data within said encodedvideo stream utilizing at least one of a fixed length coding (FLC)process, a variable length coding (VLC) process and a context adaptivebinary arithmetic coding (CABAC) process.
 99. The method according toclaim 92, comprising, if said determined identifier corresponds to VC-1video encoding, decoding said at least a portion of said receivedpacketized data utilizing at least one of a FLC process and a VLCprocess.
 100. The method according to claim 92, comprising, if saiddetermined identifier corresponds to at least one of an H.261, H.263,H.263+, MPEG-1, MPEG-2 and MPEG-4 video encoding, decoding said at leasta portion of said received packetized data utilizing at least one of aFLC process and a VLC process.
 101. The method according to claim 92,wherein said decoded corresponding portions of said encoded video streamcomprises at least one of prediction pixels information and predictionerror information.
 102. The method according to claim 92, comprisinggenerating a decoded video stream utilizing at least a portion of saiddecoded corresponding portions of said encoded video stream.
 103. Themethod according to claim 92, comprising, for each of said identifiedone or more corresponding CODECs, decoding said at least a portion ofsaid received packetized data utilizing at least one of inversetransformation, inverse quantization, and motion compensation.
 104. Asystem for processing video, the system comprising: one or moreprocessors and/or circuits in a chip, said one or more processors and/orcircuits being operable to: parse an encoded video stream to determineone or more identifiers that identifies one or more corresponding CODECto be utilized for decoding one or more corresponding portions of saidencoded video stream; and decode corresponding portions of said encodedvideo stream utilizing said identified one or more corresponding CODECs.105. The system according to claim 104, wherein said one or moreprocessors and/or circuits are operable to concurrently decode saidcorresponding portions of said encoded video stream utilizing saididentified one or more corresponding CODECs
 106. The system according toclaim 104, wherein said one or more processors and/or circuits areoperable to select from a plurality of CODECs, said one or morecorresponding CODECs to be utilized for said decoding of said one ormore corresponding portions of said encoded video stream.
 107. Thesystem according to claim 104, wherein said one or more processorsand/or circuits are operable to determine a start code within receivedpacketized data of said encoded video stream, wherein said start codeseparates packets within said encoded video stream.
 108. The systemaccording to claim 107, wherein said one or more processors and/orcircuits are operable to match a plurality of bytes within said receivedpacketized data with a determined byte sequence.
 109. The systemaccording to claim 108, wherein said one or more processors and/orcircuits are operable to remove said plurality of bytes from saidreceived packetized data, if said plurality of bytes matches saiddetermined byte sequence.
 110. The system according to claim 104,wherein said one or more processors and/or circuits are operable todecode said at least a portion of said received packetized data withinsaid encoded video stream utilizing at least one of a fixed lengthcoding (FLC) process, a variable length coding (VLC) process and acontext adaptive binary arithmetic coding (CABAC) process, if saiddetermined identifier corresponds to H.264 video encoding.
 111. Thesystem according to claim 104, wherein said one or more processorsand/or circuits are operable to decode said at least a portion of saidreceived packetized data utilizing at least one of a FLC process and aVLC process, if said determined identifier corresponds to VC-1 videoencoding.
 112. The system according to claim 104, wherein said one ormore processors and/or circuits are operable to decode said at least aportion of said received packetized data utilizing at least one of a FLCprocess and a VLC process, if said determined identifier corresponds toat least one of an H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 videoencoding.
 113. The system according to claim 104, wherein said one ormore processors and/or circuits are operable to decode correspondingportions of said encoded video stream comprises at least one ofprediction pixels information and prediction error information.
 114. Thesystem according to claim 104, wherein said one or more processorsand/or circuits are operable to generate a decoded video streamutilizing at least a portion of said decoded corresponding portions ofsaid encoded video stream.
 115. The system according to claim 104,comprising, for each of said identified one or more correspondingCODECs, decoding said at least a portion of said received packetizeddata utilizing at least one of in verse transformation, inversequantization, and motion compensation.